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preliminary this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results. 1850 ramtron drive, colorado springs, co 80921 (800) 545 - fram, (719) 481 - 7000 rev. 1.3 http://www.ramtron.com july 2011 page 1 of 13 fm 24w256 256kb wide voltage serial f - ram features 256k bit ferroelectric nonvolatile ram ? organized as 32,768 x 8 bits ? high endurance 100 trillion (10 14 ) read/writes ? 38 year data retention ( @ +75oc) ? nodelay? writes ? advanced high - reliability ferroelectr ic process fast two - wire serial interface ? up to 1 mhz maximum bus frequency ? direct hardware replacement for eeprom ? supports legacy timing for 100 khz & 400 khz low power operation ? wide voltage operation 2.7v - 5.5 v ? 10 0 ? a active current (100 khz) ? 15 ? a standby current ( typ. ) industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green/rohs soic package s description the fm 24w256 is a 256 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric ra ndom access memory or f - ram is nonvolatile and performs reads and writes like a ram. it provide s reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. the fm 24w256 performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after it has been successfully transferred to the device. the next bus cycle may commence immediately without th e need for data polling. in addition, the product offers substantial write endurance compared with other nonvolatile memories. the fm24w256 is capable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom . these capabili ties make the fm 24w256 ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with less overhead for the system. the fm 24w256 provides substantial benefits to users of serial eeprom, yet these benefits are available in a hardware drop - in repla cement . the fm 24w256 is available in industry stan dard 8 - pin soic package using a familiar two - wire protocol. it is guaranteed over an ind ustrial temperature range of - 40c to +85c. pin configuration pin names function a0 - a2 device select address sda serial data/ a ddress scl serial clock wp write protect vss ground vdd supply voltage ordering information fm 24w256 - g 8 - pin green /rohs soic fm 24w256 - gtr 8 - pin green/rohs soic, tape & reel fm24w256 - eg * 8 - pin green/roh s eiaj soic fm24w256 - egtr * 8 - pin green/rohs eiaj soic, tape & reel * n ot recommended for new designs a 0 a 1 a 2 vss vdd wp scl sda 1 2 3 4 8 7 6 5
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 2 of 14 figure 1. block diagram pin description pin name type pin description a0 - a2 input device select address 0 - 2: these pins are used to select one of up to 8 devices of the same type on the same two - wire bus. to select the device, the address value on the three pins must match the correspond ing bits contained in the slave address. the address pins are pulled down internally. sda i/o serial data/ address : t his is a bi - directional pin for the two - wire interface. it is open - drai n and is intended to be wire - or d with other devices on the two - wire bus. the input buffer incorporates a s chmitt trigger for noise immunity and the output driver includes slope control for falling edges. a pull - up resistor is required. scl input serial clock: the serial clock pin for the two - wire interface. data is clocked out of the part on the falling edge, and in to the device on the rising edge. the scl input also incorporates a sch mitt trigger input for noise immunity. wp input write protect: when tied to vdd, addresses in the entire memory map will be write - protected. when wp is connected to ground, all addresses may be written. this pin is pulled down internally. vdd supply sup ply voltage: 2.7v to 5.5 v vss supply ground address latch 4 , 096 x 64 fram array data latch 8 sda counter serial to parallel converter control logic scl wp a 0 - a 2
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 3 of 13 overview the fm 24w256 is a serial f - ram memory. the memory array is logically organized as a 32,768 x 8 bit memory array and is accessed using an industry standard two - wire interface. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm 24w256 and a serial eeprom with the same pinout relates to its superior write performance. memory architecture when accessing the fm 24w256 , the user addresses 32,768 locations each with 8 data bits. these data bits are shifted serially. the 32,768 addresses are accessed using the two - wire protocol, which includes a slave address (to distinguish other non - mem ory devices), and a 2 - byte address. only t he lower 15 bits are used by the d ecoder for accessing the m emory. the upper most address bit should be set to 0 for compatibility with higher density devices in the future. the access time for memory operation is essentially zero beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the two - wire bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious system benefits from the fm 24w256 due to its fast write cycle and high endurance as compared with eeprom. however there are less ob vious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during m uch of the cycle. note that it is the users responsibility to ensure that v dd is within data sheet tolerances to prevent incorrect operation. two - wire interface the fm 24w256 employs a bi - directional two - wire bus protocol using few pins or board space. figure 2 illustrates a typical system configuration using the fm 24w256 in a microcontroller - based system. the industry standard two - wire bus is familiar to many users but is described in this section. by convention, any device that is sending data onto t he bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being control led is a slave. the fm 24w256 always is a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. figure 3 illustrates the signal conditions t hat specify the four states. detailed timing diagrams are in the electrical specifications. figure 2. typical system configuration microcontroller sda scl fm 24 w 256 a 0 a 1 a 2 sda scl fm 24 w 256 a 0 a 1 a 2 vdd r min = 1 . 1 kohm r max = t r / cbus
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 4 of 13 figure 3. data transfer protocol stop condition a stop c ondition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the fm 24w256 should end with a stop condition. if an operation is in progress when a stop is asserted, the operation will be aborted. t he master must have control of sda (not a memory read) in order to assert a stop condition. start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all commands should be preceded by a s tart condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm 24w256 for a new operation. if during operation the power supply drops below the specifie d v dd minimum, the system should issue a start condition prior to performing another operation. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the two conditions described above, the sd a signal should not change while scl is high. acknowledge the acknowledge takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the recei ver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no - acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fails. in this case, the no - acknowledge ceases the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowl edge to deliberately end an operation. for example, during a read operation, the fm 24w256 will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). when a read operation is complete and no more data is needed, the re ceiver must not acknowledge the last byte. if the receiver acknowledges the last byte, this will cause the fm 24w256 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. slave address the first byte that the fm 24w256 expects after a start condition is the slave address. as shown in figure 4, the slave address contains the device type, the device select address bits, and a bit that specifies if the transaction is a read or a write. bits 7 - 4 are the device ty pe and should be set to 1010b for the fm 24w256 . these bits allow other types of function types to reside on the 2 - wire bus within an identical address range. bits 3 - 1 are the address select bits. they must match the corresponding value on the external addr ess pins to select the device. up to eight fm 24w256 s can reside on the same two - wire bus by assigning a different address to each. bit 0 is t he read/write bit. r/w=1 indicates a read operation and r/w=0 indicates a write operation. stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 5 of 13 figure 4. slave address addressing overview after the fm 24w256 (as receiver) acknowledges the slave address , the master can place the memory address on the bus for a write operation. the address requires two bytes. the first is the msb. since the device uses only 1 5 address bi ts, the value of the upper bit is dont care . following the msb is the lsb with the remaining eight address bits. the address value is latched internally. each access causes the latched address value to be incremented automa tically. the current address is the value that is held in the latch -- either a newly written value or the address following the last access. the current address will be held for as long as power remains or until a new value is written. reads always use th e current address. a random read address can be loaded by beginning a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm 24w256 increments the internal address latch. this allows the next sequen tial byte to be accessed with no additional addressing. after the last address ( 7fff h) is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. data transfe r after the address information has been transmitted, data transfer between the bus master and the fm 24w256 can begin. for a read operation the fm 24w256 will place 8 data bits on the bus then wait for an acknowledge from the master. if the acknowledge occu rs, the fm 24w256 will transfer the next sequential byte. if the acknowledge is not sent, the fm 24w256 will end the read operation. for a write operation, the fm 24w256 will accept 8 data bits from the master then send an acknowledge. all data transfer occur s msb (most significant bit) first. memory operation the fm 24w256 is designed to operate in a manner very similar to other 2 - wire interface memory products. the major differences result from the higher performance write capability of f - ram technology. th ese improvements result in some differences between the fm 24w256 and a similar configuration eeprom during writes. the complete operation for both writes and reads is explained below. write operation all writes begin with a slave address , then a memory ad dress. the bus master indicates a write operation by setting the lsb of the slave address to a 0. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may b e written. if the end of the address range is reached internally, the address counter will wrap from 7fff h to 0000h. unlike other nonvolatile memory technologies, there is no effective write delay with f - ram . since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or write can occur immediately following a write. acknowledge pollin g, a technique used with eeproms to determine if a write is complete is unnecessary and will always return a ready condition. internally, an actual memory write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is s ent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8 th data bit. the fm 24w256 uses no page buffering. the memory array can be write protected using the wp pin. setting the wp pin to a high condition (v dd ) will write - protect all addresses. the fm 24w256 will not acknowledge data bytes that are written to protected addresses. in addition, the address counter will not increment if writes are attempted to the se addresses. setting wp to a low state (v ss ) will deactivate this feature. wp is pulled down internally. figure s 5 and 6 below illustrate a single - byte and multiple - byte write cycles . 1 0 1 0 a2 r/w slave id 7 6 5 4 3 2 1 0 a1 a0 device select
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 6 of 13 figure 5. single byte write figure 6. multiple byte write read operation there are two basic types of read operations. they are current address read and selective address read. in a current address read, the fm 24w256 uses the internal address latch to sup ply the address. in a selective read, the user performs a procedure to set the address to a specific value. current address & sequential read as mentioned above the fm 24w256 uses an internal latch to supply the address for a read operation. a current addr ess read uses the existing value in the address latch as a starting place for the read operation. the system reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave addre ss with the lsb set to 1. this indicates that a read operation is requested. after receiving the complete slave address , the fm 24w256 will begin shifting out data from the current address on the next clock. the current address is the value held in the inte rnal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. each time the bus master acknowledges a byte, this indicates that the fm 24w256 should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus co ntention as the fm 24w256 attempts to read out additional data onto the bus. the four valid methods are: 1. the bus master issues a no - acknowledge in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below. this is pr eferred. 2. the bus master issues a no - acknowledge in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. 4. the bus master issues a start in the 9 th clock cycle. if the internal address reaches 7fff h, it will wr ap around to 0000h on the next read cycle. figures 7 and 8 below show the proper operation for current address reads. selective (random) read there is a simple technique that allows a user to select a random address location as the starting point for a re ad operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the address bytes that are s a slave address 0 address msb a data byte a p by master by fm 24 w 256 start address & data stop acknowledge address lsb a x s a slave address 0 address msb a data byte a p by master by fm 24 w 256 start address & data stop acknowledge address lsb a data byte a x
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 7 of 13 loaded into the internal address latch. after the fm 24w256 acknowledges the address, the bus master issues a start condition. this simultaneously abor ts the write operation and allows the read command to be issued with the slave address lsb set to a 1 . the operation is now a current address read. figure 7. current address read figure 8. sequential read figure 9. selective (random) read s a slave address 1 data byte 1 p by master by fm 24 w 256 start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by fm 24 w 256 start address stop acknowledge no acknowledge data data byte a acknowledge s a slave address 1 data byte 1 p by master by fm 24 w 256 start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a x
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 8 of 13 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1. 0v to +7 .0v v in voltage on any pin with respect to v ss - 1.0v to +7 .0v and v in < v dd +1.0v * t stg storage temperature - 55 ? c to +12 5 ? c t lead lead t emperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model ( aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 3.5kv 1.25kv 200v package moisture sensitivity level msl - 1 (soic) msl - 2 (eiaj) * exception: the v in < v dd +1.0v restriction does not apply to the scl and sda inputs. stresses above those l isted under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. dc operating conditions (t a = - 40 ? c to + 85 ? c, v dd =2.7v to 5.5 v unless otherwise specified) symbol parameter min typ max units notes v dd m ain power supply 2.7 3.3 5.5 v i dd v dd supply current @ scl = 100 khz @ scl = 400 khz @ scl = 1 mhz 100 20 0 4 00 ? a ? a ? a 1 i sb standby current 15 3 0 ? a 2 i li input leakage current 1 ? a 3 i lo output leakage current 1 ? a 3 v il input l ow voltage - 0.3 0.3* v dd v v ih input high voltage 0.7* v dd v dd + 0.3 v v ol output low voltage @ i ol = 3.0 ma 0.4 v r in address input resistance (wp, a2 - a0) for v in = v il (max) for v in = v ih (min) 4 0 4 k ? m ? 4 notes 1. scl toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. scl = sda = v dd . all inputs v ss or v dd . stop command issued. 3. v in or v out = v ss to v dd . does not apply to wp, a2 - a0 pins . 4. the inpu t pull - down circuit is strong (4 0k ? ) when the input voltage is below v il an d wea k (4 m ? ) when the input voltage is above v ih .
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 9 of 13 a c parameters (t a = - 40 ? c to + 85 ? c, v dd =2.7v to 5.5 v unless otherwise specified) symbol parameter min max min max min max units notes f scl scl clock frequency 0 100 0 400 0 1000 khz 1 t low clock low per iod 4.7 1.3 0.6 ? s t high clock high period 4.0 0.6 0.4 ? s t aa scl low to sda data out valid 3 0.9 0.55 ? s t buf bus free before new transmission 4.7 1.3 0.5 ? s t hd:sta start condition hold time 4.0 0.6 0.25 ? s t su:sta start conditio n setup for repeated start 4.7 0.6 0.25 ? s t hd:dat data in hold 0 0 0 ns t su:dat data in setup 250 100 100 ns t r input rise time 1000 300 300 ns 2 t f input fall time 300 300 100 ns 2 t su:sto stop condition setup 4.0 0.6 0.25 ? s t dh data output hold (from scl @ v il ) 0 0 0 ns t sp noise suppression time constant on scl, sda 50 50 50 ns notes : all scl specifications as well as start and stop conditions apply to both read and write operations. 1 the speed - related specific ations are guaranteed characteristic points along a continuous curve of operation from dc to 1 mhz. 2 this parameter is periodically sampled and not 100% tested. capacitance (t a = 25 ? c, f=1.0 mhz, v dd = 3v) symbol parameter max units notes c i/o input/ o u tput c apacitance (sda) 8 pf 1 c in input c apacitance 6 pf 1 notes 1 this parameter is periodically sampled and not 100% tested. power cycle timing power cycle timing ( t a = - 40 ? c to +85 ? c, v dd = 2.7v to 5.5 v unless otherwis e specified ) symbol parameter min max units notes t pu power up (v dd min) to first access (start condition ) 1 0 - ms t pd last access (stop condition ) to power down (v dd min) 0 - ? s t vr v dd rise time 3 0 - ? s/v 1 t vf v dd fall time 10 0 - ? s/v 1 not es 1. sl ope measured at any point on v dd waveform. v d d m i n . v d d s d a , s c l t v r t p d t p u t v f
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 10 of 13 ac test conditions equivalent ac load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters a pply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant datasheet sections . these diagrams illustrate the timing parameters only. read bus timing write bus timing data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 19 - years @ +75oc 38 - years t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:d at t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda 5.5v output 1700 ? 100 pf
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 11 of 13 mechanical drawing 8 - pin soic (jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xx xx xx= part number, p= package type (g=soic, eg=eiaj soic) r=rev code, ll l llll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 24w256 , green soic package, y ear 2010, work week 37 fm 24w256 - g a 00002g1 ric1037 xxxx xxx - p r ll l l ll l ricyyww p i n 1 3 . 9 0 0 . 1 0 6 . 0 0 0 . 2 0 4 . 9 0 0 . 1 0 0 . 1 0 0 . 2 5 1 . 3 5 1 . 7 5 0 . 3 3 0 . 5 1 1 . 2 7 0 . 1 0 m m 0 . 2 5 0 . 5 0 4 5 0 . 4 0 1 . 2 7 0 . 1 9 0 . 2 5 0 - 8 r e c o m m e n d e d p c b f o o t p r i n t 7 . 7 0 0 . 6 5 1 . 2 7 2 . 0 0 3 . 7 0
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 12 of 13 8 - pin eiaj soic (wide body) all dimensions in millimeters . eiaj soic package marking scheme legend: xxxxxx= part number, p= package type (g=soic, eg=eiaj soic) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm24w256, green eiaj soic package, year 2010, work week 37 fm24w256 - e g a 00002g1 ric1037 xxxx xxx - p r ll llll l ric yyww pin 1 5 . 28 0 . 10 8 . 00 0 . 25 5 . 23 0 . 10 0 . 05 0 . 25 1 . 78 2 . 00 0 . 36 0 . 50 1 . 27 0 . 10 mm 0 . 51 0 . 76 0 . 19 0 . 25 0 ? - 8 ? recommended pcb footprint 9 . 30 0 . 65 1 . 27 2 . 15 5 . 00 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e r n a t i v e : f m 2 4 w 2 5 6 - g
fm24w256 - 256kb wide voltage i2c f - ram rev. 1.3 july 2011 page 13 of 13 revision history revision date summary 1.0 11/19 /2010 initial release 1.1 1/17/2011 added esd ratings. changed v ih (max) to v dd +0.3v. 1.2 2/15 /2011 changed to msl - 2 for eiaj package. changed t pu and t vf spec limit s. 1.3 7/12/2011 eiaj package is not recommended for new designs (nrnd).

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